1. Field of the Invention
The present invention relates to a semiconductor device, a method of manufacturing the same, and a method of evaluating a semiconductor device.
2. Description of the Related Art
In recent years, semiconductor devices including LSIs and the like have been miniaturized. However, the improvement of the performance of MOS transistors by miniaturization is approaching a limit. Attempts to improve the performance in a generally used MOS transistor by modifying the structure thereof are being made. As one of such attempts, there is a method in which the mobility of carriers is improved by applying appropriate stress to a channel region of the MOS transistor. There are various ways to apply the stress. In Non-Patent Document 1, recesses are formed in a silicon substrate on both sides of a gate electrode, and SiGe layers to be used as source/drain electrodes are epitaxially grown in the recesses, thus introducing strain into a channel by utilizing a difference in lattice constant between silicon and SiGe. According to Non-Patent Document 1, this structure is said to have the significant effect in that the drive current of a p-type MOS transistor is improved by 10% or more.
Moreover, in addition to Non-Patent Document 1, technologies related to the present invention are also disclosed in Patent Documents 1 to 4.
(Patent Document 1) Japanese Unexamined Patent Publication No. Sho 58 (1983)-35938
(Patent Document 2) Japanese Unexamined Patent Publication No. Hei 4 (1992)-180633
(Patent Document 3) Japanese Unexamined Patent Publication No. Hei 7 (1995)-50293
(Patent Document 4) WO98/40909 International Publication Pamphlet
(Non-Patent Document 1) T. Ghani et al., “A 90 nm High Volume Manufacturing Logic Technology Featuring Novel 45 nm Gate Length Strained Silicon CMOS Transistors,” IEDM Tech Dig., pp. 978-980, (2003)
Incidentally, in the structure disclosed in Non-Patent Document 1, stress is applied to the channel from the SiGe layers as described previously. If the amount of the stress is nonuniform in the gate width direction or varies among transistors, this transistor cannot be produced in volume to be widely used.
Moreover, not only in the MOS transistor disclosed in Non-Patent Document 1, but also in a general MOS transistor in which recesses for SiGe layers are not formed in a silicon substrate, when a new device or the like is developed, a test MOS transistor is fabricated, and characteristics thereof are evaluated. Among a number of characteristics, a carrier distribution in a channel greatly influences the performance of a transistor. Accordingly, it is preferable that the carrier distribution is directly measured. However, a method of measuring the carrier distribution has not been established so far.